论文标题
FPGA技术影响的建筑分析
Architectural Analysis of FPGA Technology Impact
论文作者
论文摘要
高级语言在设计硬件上的使用正在越来越受欢迎，因为它们通过提供更高的抽象来提高设计生产率。但是，这种抽象水平的一个缺点是将低级实现问题与原始高级设计联系起来的困难，这对于体系结构优化至关重要。在这项工作（2013年4月至2014年4月之间）中，我们提出了一种方法，以分析技术对建筑的影响，并生成建筑层面，延迟和电力指标。这种反馈使设计师可以快速衡量建筑决策对生成硬件质量的影响，并为自动建筑分析打开了大门。我们使用两种设计在三个FPGA平台上使用技术的使用：芦苇 - 固体错误校正解码器和32位管道的处理器实现。
The use of high-level languages for designing hardware is gaining popularity since they increase design productivity by providing higher abstractions. However, one drawback of such abstraction level has been the difficulty of relating the low-level implementation problems back to the original high-level design, which is paramount for architectural optimization. In this work (developed between April 2013 and April 2014), we propose a methodology to analyze the effects of technology over the architecture, and to generate architectural-level area, delay and power metrics. Such feedback allows the designer to quickly gauge the impact of architectural decisions on the quality of generated hardware and opens the door to automatic architectural analysis. We demonstrate the use of our technique on three FPGA platforms using two designs: a Reed-Solomon error correction decoder and a 32-bit pipelined processor implementation.
