论文标题

可穿戴的CMOS生物传感器,具有3种能源分辨率可扩展时间的电阻的数字转换器的电阻

A Wearable CMOS Biosensor with 3 Designs of Energy-Resolution Scalable Time-Based Resistance to Digital Converter

论文作者

Seo, Dong-Hyun, Chatterjee, Baibhab, Scott, Sean, Valentino, Daniel, Peroulis, Dimitrios, Sen, Shreyas

论文摘要

本文介绍了可穿戴CMOS生物传感器的设计和分析,具有三种不同设计的能量分辨率可扩展的基于时间的基于时间转换器的电阻(RDC),旨在最小化能量/转换步骤或最大化位分辨率。实现的RDC由一个3阶段的差分环振荡器组成,该振荡器的电流用电阻传感器饿死,单端放大器的差速器,外芯片柜台和串行界面。第一个设计RDC包括基于时间的RDC的基本结构和针对性的低能/转换步骤。与第一个设计RDC相比,第二个设计RDC旨在通过加速闩锁的帮助来改善振荡器的RMS抖动/相位噪声,以实现更高的位分辨率。第三个设计RDC通过通过改进的相位设计来扩展技术来降低功耗,从而达到了第二次设计RDC的1位更好分辨率。使用基于时间的实现,RDCS具有能量分辨率的缩放性,并消耗861NW,在TSMC 0.35UM技术中设计1中分辨率为18位。设计2和3分别使用TSMC 0.35UM消耗20位分辨率的19.1UW,分别使用TSMC 0.18UM的20位分辨率消耗17.6UW(两者都有10ms读取时间,每秒重复一次)。 Design 3具有30毫秒的读取时间,可实现21位分辨率,这是报告基于时间的ADC的最高分辨率。基于0.35UM的RDC是报告的最低功率的ADC,而基于速度锁存的0.18UM基于时间的RDC可提供最高分辨率。所有3设计的活动芯片面积小于1.1 mm^2。

This paper presents the design and analysis of a wearable CMOS biosensor with three different designs of energy-resolution scalable time-based resistance to digital converters (RDC), targeted towards either minimizing the energy/conversion step or maximizing bit-resolution. The implemented RDCs consist of a 3-stage differential ring oscillator which is current starved with the resistive sensor, a differential to single ended amplifier, an off-chip counter and serial interface. The first design RDC included the basic structure of time-based RDC and targeted low energy/conversion step. The second design RDC aimed to improve the rms jitter/phase noise of the oscillator with help of speed-up latches, to achieve higher bit-resolution as compared to the first design RDC. The third design RDC reduced the power consumption by scaling the technology with the improved phase-noise design, achieving 1-bit better resolution as that of the second design RDC. Using a time-based implementation, the RDCs exhibit energy-resolution scalablity, and consume 861nW with 18-bit resolution in design 1 in TSMC 0.35um technology. Design 2 and 3 consume 19.1uW with 20-bit resolution using TSMC 0.35um, and 17.6uW with 20-bit resolutions using TSMC 0.18um, respectively (both with 10ms read-time, repeated every second). With 30ms read-time, design 3 achieves 21-bit resolution, which is the highest resolution reported for a time-based ADC. The 0.35um time-based RDC is the lowest-power time-based ADC reported, while the 0.18um time-based RDC with speed-up latch offers the highest resolution. The active chip-area for all 3-designs are less than 1.1 mm^2.

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