论文标题
Spiker：用于尖峰神经网络的FPGA优化硬件加速度
Spiker: an FPGA-optimized Hardware acceleration for Spiking Neural Networks
论文作者
论文摘要
尖峰神经网络（SNN）是一种生物学上合理和有效的人工神经网络（ANN）的新兴类型。这项工作介绍了用于高性能推断的SNN的硬件加速器的开发，针对Xilinx Artix-7现场可编程门阵列（FPGA）。神经元内使用的模型是泄漏的集成和火（LIF）。执行是时钟驱动的，这意味着即使在没有尖峰的情况下，神经元的内部状态也会在每个时钟周期更新。使用MINST数据集评估加速器的推断功能。该培训是在完整的精确模型上离线进行的。结果表明，如果与最先进的加速器相比，性能有很好的改善，每个图像需要215μs。能源消耗略高于最优化的设计，每个图像的平均值为13MJ。测试设计由四百个神经元的单层组成，并在FPGA上使用了大约40％的可用资源。这使其适用于边缘的时期应用程序，为FPGA上的其他加速任务留出空间。
Spiking Neural Networks (SNN) are an emerging type of biologically plausible and efficient Artificial Neural Network (ANN). This work presents the development of a hardware accelerator for a SNN for high-performance inference, targeting a Xilinx Artix-7 Field Programmable Gate Array (FPGA). The model used inside the neuron is the Leaky Integrate and Fire (LIF). The execution is clock-driven, meaning that the internal state of the neuron is updated at every clock cycle, even in absence of spikes. The inference capabilities of the accelerator are evaluated using the MINST dataset. The training is performed offline on a full precision model. The results show a good improvement in performance if compared with the state-of-the-art accelerators, requiring 215μs per image. The energy consumption is slightly higher than the most optimized design, with an average value of 13mJ per image. The test design consists of a single layer of four-hundred neurons and uses around 40% of the available resources on the FPGA. This makes it suitable for a time-constrained application at the edge, leaving space for other acceleration tasks on the FPGA.
