论文标题
A 1.5GS/S 8B管道上的SAR ADC具有14nm CMOS中的输出水平转移沉降技术
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS
论文作者
论文摘要
单个通道1.5gs/s 8位管道的SAR ADC利用新颖的输出水平转移（OLS）沉降技术来降低动力的功率并实现动态残基放大器的低压操作。 ADC由4位第一阶段和5位第二阶段组成，其1位冗余，以放松第一阶段的偏移，增益和结算要求。采用OLS技术允许从动态残基放大器中获得〜4的增益，而沉降时间仅为常规CML放大器的28％。通过在两个异步阶段使用并行比较器的使用，ADC的转换速度进一步提高。 ADC用14nm FinFET技术制造，占据了0.0013mm2核心区域，并以0.8V的电源运行。在消耗2.4MW的同时，在Nyquist实现6.6位应附的应附力，导致16.7fj/cons.-Step。
A single channel 1.5GS/s 8-bit pipelined-SAR ADC utilizes a novel output level shifting (OLS) settling technique to reduce the power and enable low-voltage operation of the dynamic residue amplifier. The ADC consists of a 4-bit first stage and a 5-bit second stage, with 1-bit redundancy to relax the offset, gain, and settling requirements of the first stage. Employing the OLS technique allows for an inter-stage gain of ~4 from the dynamic residue amplifier with a settling time that is only 28% of a conventional CML amplifier. The ADC's conversion speed is further improved with the use of parallel comparators in the two asynchronous stages. Fabricated in a 14nm FinFET technology, the ADC occupies 0.0013mm2 core area and operates with a 0.8V supply. 6.6-bit ENOB is achieved at Nyquist while consuming 2.4mW, resulting in an FOM of 16.7fJ/conv.-step.
