论文标题
X型不良：故障对具有逻辑计算的Memristor-Crossbar阵列中二进制神经网络的影响
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation
论文作者
论文摘要
基于Memristor的横梁阵列代表了一种有希望的新兴记忆技术，可以通过提供高密度并启用内存计算（CIM）范式来替代传统记忆。尽管模拟计算提供了基于Memristor的CIM的最佳性能，非理想性和ADC/DAC转换极限。逻辑中的逻辑（LIM）提出了CIM的另一种味道，其中，以二进制方式使用了回忆录来实现逻辑门。由于二进制神经网络（BNNS）使用二进制逻辑门作为主要操作，因此它们可以从二进制操作的大规模平行执行中受益，并且可以更好地弹性，从而更好地弹性。尽管已经对传统的神经网络进行了彻底的研究，但故障对基于备忘录的BNN的影响尚不清楚。因此，我们分析了故障对基于Memristor的横杆阵列中BNN的逻辑门的影响。我们提出了一个模拟框架，该框架模拟了不同的传统故障，以检查Memristive横杆阵列中BNN的准确性损失。此外，我们根据加速AI应用的鲁棒性和可行性比较了不同的逻辑系列。
Memristor-based crossbar arrays represent a promising emerging memory technology to replace conventional memories by offering a high density and enabling computing-in-memory (CIM) paradigms. While analog computing provides the best performance, non-idealities and ADC/DAC conversion limit memristor-based CIM. Logic-in-Memory (LIM) presents another flavor of CIM, in which the memristors are used in a binary manner to implement logic gates. Since binary neural networks (BNNs) use binary logic gates as the dominant operation, they can benefit from the massively parallel execution of binary operations and better resilience to variations of the memristors. Although conventional neural networks have been thoroughly investigated, the impact of faults on memristor-based BNNs remains unclear. Therefore, we analyze the impact of faults on logic gates in memristor-based crossbar arrays for BNNs. We propose a simulation framework that simulates different traditional faults to examine the accuracy loss of BNNs on memristive crossbar arrays. In addition, we compare different logic families based on the robustness and feasibility to accelerate AI applications.
