论文标题
混淆数字IP的层次结构
Obfuscating the Hierarchy of a Digital IP
论文作者
论文摘要
综合电路(IC)生态系统中不受信任的参与者出现了许多安全威胁。其中,有意伪造,生产或修改IC的逆向工程实践令人担忧。近年来,已经提出了各种技术来减轻上述威胁,但似乎没有任何技术足以掩盖设计的层次结构。这种混淆层次结构的能力对于包含重复模块的设计尤为重要。在本文中,我们提出了一种新颖的方式来通过利用常规逻辑合成来混淆此类设计。我们利用合成工具中可用于创建设计多样性的多个优化。我们使用DANA逆向工程工具执行的安全分析证实了这些优化对混淆的重大影响。在众多被认为是混淆的设计实例中,用户可以找到可以产生非常小的开销的选项,同时仍使反向工程师的工作混淆。
Numerous security threats are emerging from untrusted players in the integrated circuit (IC) ecosystem. Among them, reverse engineering practices with the intent to counterfeit, overproduce, or modify an IC are worrying. In recent years, various techniques have been proposed to mitigate the aforementioned threats but no technique seems to be adequate to hide the hierarchy of a design. Such ability to obfuscate the hierarchy is particularly important for designs that contain repeated modules. In this paper, we propose a novel way to obfuscate such designs by leveraging conventional logic synthesis. We exploit multiple optimizations that are available in the synthesis tool to create design diversity. Our security analysis, performed by using the DANA reverse engineering tool, confirms the significant impact of these optimizations on obfuscation. Among the many considered obfuscated design instances, users can find options that incur very small overheads while still confusing the work of a reverse engineer.