论文标题
PMUSPILL:泄漏SGX保护秘密的性能监视器单元中的计数器
PMUSpill: The Counters in Performance Monitor Unit that Leak SGX-Protected Secrets
论文作者
论文摘要
性能监视器单元(PMU)是当前处理器上的重要硬件模块,它将处理器启动的事件计入一组PMU计数器。理想情况下,由执行的指令触发的事件,但结果未成功(暂时执行)。但是,在这项研究中,我们发现瞬态执行说明触发的一些PMU事件实际上将由PMU记录。基于此,我们提出了PMUSPILL攻击,该攻击使攻击者能够恶意泄露暂时执行期间加载的秘密数据。最大的挑战是如何将秘密数据编码为PMU事件。我们构建了一个指令小工具来解决这一挑战,该挑战的执行路径可以由PMU计数器识别,代表了秘密数据的值。我们成功地实施了PMUSPILL攻击,以泄露通过实际实验中存储在Intel Software Guard Extensions(SGX)(Intel处理器中的可信执行环境(TEE))中的秘密数据。此外,我们通过迭代所有有效的PMU计数器和说明来找到脆弱的PMU计数器及其触发说明。实验结果表明,有最多20个PMU计数器可用于实施PMUSPILL攻击。我们还提供了一些可能的基于硬件和基于软件的对策来解决PMUSPILL攻击,这些攻击可用于增强未来处理器的安全性。
Performance Monitor Unit (PMU) is a significant hardware module on the current processors, which counts the events launched by processor into a set of PMU counters. Ideally, the events triggered by instructions that are executed but the results are not successfully committed (transient execution) should not be recorded. However, in this study, we discover that some PMU events triggered by the transient execution instructions will actually be recorded by PMU. Based on this, we propose the PMUSpill attack, which enables attackers to maliciously leak the secret data that are loaded during transient executions. The biggest challenge is how to encode the secret data into PMU events. We construct an instruction gadget to solve this challenge, whose execution path that can be identified by PMU counters represents what values the secret data are. We successfully implement the PMUSpill attack to leak the secret data stored in Intel Software Guard Extensions (SGX) (a Trusted Execution Environment (TEE) in the Intel's processors) through real experiments. Besides, we locate the vulnerable PMU counters and their trigger instructions by iterating all the valid PMU counters and instructions. The experiment results demonstrate that there are up to 20 PMU counters available to implement the PMUSpill attack. We also provide some possible hardware and software-based countermeasures for addressing the PMUSpill attack, which can be utilized to enhance the security of processors in future.