论文标题
不要cweat：在硬件设计的早期阶段迈向CWE分析技术
Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design
论文作者
论文摘要
为了帮助防止硬件安全漏洞传播到较晚的设计阶段，在此阶段固定昂贵，至关重要的是尽早确定安全问题，例如在RTL设计中。在这项工作中，我们研究了在Verilog源文件上运行的一组安全性扫描仪的实际含义和可行性。扫描仪表示代码的一部分可能包含一组Miter的常见弱点之一（CWES）。我们探索CWE数据库以表征CWES的范围和属性，并识别可与静态分析相配的范围。我们原型扫描仪并在11种开源设计中对它们进行了评估-4个芯片系统（SOC）和7个处理器核心 - 并探索已确定的弱点的性质。我们的分析报道了hack@dac-21中使用的OpenPiton SoC中有53个潜在弱点，其中11个我们确认为安全问题。
To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible, such as in RTL designs. In this work, we investigate the practical implications and feasibility of producing a set of security-specific scanners that operate on Verilog source files. The scanners indicate parts of code that might contain one of a set of MITRE's common weakness enumerations (CWEs). We explore the CWE database to characterize the scope and attributes of the CWEs and identify those that are amenable to static analysis. We prototype scanners and evaluate them on 11 open source designs - 4 system-on-chips (SoC) and 7 processor cores - and explore the nature of identified weaknesses. Our analysis reported 53 potential weaknesses in the OpenPiton SoC used in Hack@DAC-21, 11 of which we confirmed as security concerns.
