论文标题
稀疏锤图：一个可自定义的芯片拓扑网络
Sparse Hamming Graph: A Customizable Network-on-Chip Topology
论文作者
论文摘要
具有数百至数千个核心的芯片需要芯片上可扩展的网络（NOC）。 NOC拓扑的自定义对于达到不同芯片的各种设计目标是必要的。我们介绍了稀疏的锤子图，这是一种新型的NOC拓扑，具有可调节的成本效果折衷，该拓扑基于我们确定的四个NOC拓扑设计原理。为了有效地自定义此拓扑，我们开发了一个工具链，该工具链利用近似地平面图和链接路由来提供快速准确的成本和绩效预测。我们演示了如何使用我们的方法来实现所需的成本效果权衡，同时超过成本，绩效或两者兼而有之的拓扑。
Chips with hundreds to thousands of cores require scalable networks-on-chip (NoCs). Customization of the NoC topology is necessary to reach the diverse design goals of different chips. We introduce sparse Hamming graph, a novel NoC topology with an adjustable costperformance trade-off that is based on four NoC topology design principles we identified. To efficiently customize this topology, we develop a toolchain that leverages approximate floorplanning and link routing to deliver fast and accurate cost and performance predictions. We demonstrate how to use our methodology to achieve desired cost-performance trade-offs while outperforming established topologies in cost, performance, or both.
