论文标题

实时基于可重构硬件加速的QKD帖子处理

Real time QKD Post Processing based on Reconfigurable Hardware Acceleration

论文作者

Shingala, Foram P, Venkatachalam, Natarajan, C, Selvagangai, S, Hema Priya, S, Dillibabu, Chandravanshi, Pooja, Singh, Ravindra P.

论文摘要

键蒸馏是每个量子键分配系统的重要组成部分,因为它补偿了量子通道的固有传输错误。但是,经常被忽略的后处理引擎设计的吞吐量和互操作性方面,而退出解决方案没有提供任何保证。在本文中,我们建议使用高级合成(HLS)在字段可编程栅极阵列(FPGA)中实现的高吞吐量密钥蒸馏框架。拟议的设计使用带有MAP-REDUCE编程模型的Hadoop框架来在FPGA的有限计算资源上有效地处理大量原始数据。我们提出了一种新颖的硬件积分后处理架构,可提供动态误差校正,侧通道抗性身份验证方案以及一个内置的高速加密应用程序,该应用程序使用了安全通信的密钥。我们开发了一个半自动化的高级合成框架,能够以有希望的加速处理不同的QKD协议。总体而言,实验结果表明,性能有显着改善,并且与任何离散变量QKD系统兼容。

Key Distillation is an essential component of every Quantum Key Distribution system because it compensates the inherent transmission errors of quantum channel. However, throughput and interoperability aspects of post-processing engine design often neglected, and exiting solutions are not providing any guarantee. In this paper, we propose multiple protocol support high throughput key distillation framework implemented in a Field Programmable Gate Array (FPGA) using High-Level Synthesis (HLS). The proposed design uses a Hadoop framework with a map-reduce programming model to efficiently process large chunks of raw data across the limited computing resources of an FPGA. We present a novel hardware-efficient integrated post-processing architecture that offer dynamic error correction, a side-channel resistant authentication scheme, and an inbuilt high-speed encryption application, which uses the key for secure communication. We develop a semi automated High level synthesis framework capable of handling different QKD protocols with promising speedup. Overall, the experimental results shows that there is a significant improvement in performance and compatible with any discrete variable QKD systems.

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